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Semiconductor Manufacturers: Irvine Sensors

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Semicon Taiwan 2009
September 30 -October 2, 2009, Taipei World Trade Center, Taiwan

Semicon Europa 2009
October 6-8, 2009, Messe Dresden Germany

PV Taiwan 2009
October 7-9 2009

Semicon Japan 2009
December 2 – December 4, 2009, Makuhari Messe, Chiba, Japan

Semicon Russia 2010
June 14 -16, 2010, World Trade Center, Moscow, Russia

Irvine Sensors

Location: USA



-Stacked BGA Products

  • Accommodates virtually any BGA package stacked within the same outline and footprint
  • Memory Types: DDR, DDRII, FLASH, RLDRAMII, Mobile SDRAM - 3D stacked (2 to 4 layers)
  • Applications - Server, Portable Electronics, Cell Phone, Notebooks, Digital TV, Wireless, SSR, and Single Board Computers

    -Stacked TSOP Products

  • Economical and accommodates virtually any TSOP
  • 3D stacked (2 to 8 layers)
  • Applications - Server, Portable Electronics, VME Card, SODIMM, Memory Modules and Solid State Data Recorder (SSR)

    -Neo-StackTM Technology
    For Custom Applications

  • Accommodates a variety of different chips stacked (4 to 50 layers)
  • Heterogeneous Stack (FLASH, DRAM, ASIC, SRAM)
  • Applications - Portable Electronics, Cell Phone, Embedded Systems, Military, Space, Avionics, Wearable Computer

    -Stacked Bare Die Technology
    For Custom Applications

  • Memory Types: DDR, DDRII, FLASH, RLDRAMII-3D stacked (2 to 64 layers) within the single die footprint
  • Applications - Cell Phone, Mobile Computing, SODIMM, Military and Space MCM

    Image Processing

    -VIP/Balboa Image Processing Board

  • Balboa Architecture 320 MB/s, 64MB 20 SHARC™ Processors
  • Single width, 6U Board
  • VME/RACEway™/Link Port I/O
  • Direct Video I/O (RS170, RS422
  • IPCE™ processing to 1 Tera-Op
  • DSP acceleration for large data sets: images, SAR, sonar, and geophysics
  • Cost-effective solution for both new systems and legacy system upgrades
  • Bundled RedHawk Vision software


  • Stacked IC module and interface electronics
  • Ultra-High Speed - 1012 Ops for accelerating convolution computations
  • Module contains 64 identical layers of custom analog processing ASICs that compute the inner product of an image vector and a weight (kernal) vector
  • 5-10 Watts power dissipation
  • Module size: (.5 x .5 x .5) inch3

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  • Page created: October 1, 1997
    Last modification: August 14, 2009

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